1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a technique for forming a silicon-on-insulator (SOI) structure on a semiconductor substrate.
2. Related Art
A field-effect transistor formed on an SOI substrate has been drawing attention because of its usability in terms of easy element-isolation, no latch-up phenomenon, and small source/drain junction capacitance. Especially, since a fully depleted SOI transistor enabling low power consumption and high-speed operation is easy to be driven at low voltage, researches to drive an SOI transistor in a fully depleted mode are actively carried out. A method capable of manufacturing an SOI transistor economically by forming an SOI layer on a bulk substrate (i.e. Separation by Bonding Si islands (SBSI)) is disclosed in JP-A-2005-354024 and Separation by Bonding Si islands (SBSI) for LSI Application (T. Sakai et al.), Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004). In the SBSI, a Si layer and a SiGe layer are formed on a Si substrate, and only the SiGe layer is selectively removed by using etching rate difference between Si and SiGe so as to form a cavity between the Si substrate and the Si layer. Then the Si exposed in the cavity is thermally oxidized so as to fill between the Si substrate and the Si layer with a SiO2 layer, thus forming a BOX layer between the Si substrate and the Si layer.
In the SBSI described above, the process to selectively remove the SiGe layer is important to obtain a stable yield on processes and a high yield of electric property. In a related art method, the yield on processes and the electric property are stable in a logic circuit and a memory circuit having an SOI layer of which a planar pattern has little size differences and little irregular denseness.
However, in a circuit mounting a bulk silicon device together with an SOI device, and in a circuit mounting devices employing different driving voltages, area difference and denseness difference are generally large between plane patterns of the SOI layer. Here, in a related art manufacturing method, an etching speed of the SiGe layer deteriorates in some areas due to the irregularity of the patterns (that is, the speed slows down). Especially, if the etching time is lengthened, an accelerated Si etching disadvantageously occurs. That is, in the manufacturing method in related art, in a case where a semiconductor device mounting various devices together such as a bulk silicon device and an SOI device is manufactured, an etching selectivity of a SiGe layer with respect to a Si layer partially deteriorates. Therefore, it is hard to form an SOI layer with a large area having a stable shape and an even film thickness or an SOI layer in various shapes with high yields.
In the process for etching the SiGe layer so as to form a cavity, extra etching time is required in order to prevent leaving a non-etching part of the SiGe layer. In the manufacturing method in related art, during the extra etching after the remove of the SiGe layer (that is, over-etching), an under surface of the Si layer (that is, the SOI layer) and an upper surface of the Si substrate facing the cavity get rough, disadvantageously producing irregularities thereon.
If the under surface of the SOI layer and the upper surface of the Si substrate get rough, the evenness of the film thickness of the SOI layer deteriorates. The thermal oxide film growing downward from the under surface of the SOI layer and the thermal oxide film growing upward from the upper surface of the Si substrate can not be contacted firmly at about the center in the thickness direction. Therefore, the adhesiveness of the SOI layer with respect to the Si substrate through the thermal oxide films (that is, the BOX layer) disadvantageously deteriorates. As the above, the manufacturing method in related art has been required to improve a process yield and stabilize electrical property of a semiconductor device mounting various devices together described above.